1. Field of the Invention
The present invention relates to an operational amplifier, and more particularly, to an operational amplifier with inherent direct current (DC) offset cancellation.
2. Description of the Prior Art
A fully differential operational amplifier is widely used in various high-speed applications, such as a communication system and audio/video processing system. A general fully differential amplifier consists of an input stage and an output stage, where the input stage provides high gain and the output stage provides required output swings.
Please refer to FIG. 1, which is a schematic diagram of an operational amplifier 10 according to the prior art. The operational amplifier 10 is a fully differential operational amplifier including an input stage 11 and an output stage 12. The input stage 11 includes p-type transistors MP1-MP4 and n-type transistors MN1-MN5, forming four differential pairs and a common mode feedback circuit 100 that generates an output common mode voltage of the input stage 11. The output stage 12 includes p-type transistors MP6, MP7, n-type transistors MN6, MN7, the capacitors CM1, CM2, and a common mode feedback circuit 102. Bias voltages VBP1, VBP2, VBN1, VBN2, and VBN3 are used in differential pairs in the input stage 11 and the output stage 12. The input stage 11 receives differential input signals INP and INN, and generates differential output signals VOP and VON. The output stage 12 receives the differential output signals generated by the input stage 11, and generates differential output signals OUTP and OUTN. In FIG. 1 and the following figures, the common mode feedback circuit is abbreviated to CMFB.
There are some disadvantages in the operational amplifier 10. For example, the output stage 12 has a small transconductance and a low parasitic pole resulted from the use of the transistors MP6 and MP7. Also, sink current of the output stage 12 is a fixed value due to the fixed bias voltage VBN3 that controls gate voltages of the transistors MN6 and MN7. As shown in FIG. 1, the output common mode voltage of the input stage 11 is determined by the input common mode voltage of the output stage 12, which easily results in a headroom issue that occurs in the input stage 11 and makes the transistors MP1-MP4 operate in a triode region. The output common mode voltage of the input stage 11 varies in several hundred-mV, which is influenced by the manufacturing process, supplying power, and temperature. Therefore, ideal gain is hard to achieve in a low supplying voltage design like 1.2V.
Please refer FIG. 2, which is a schematic diagram of an operational amplifier 20 according to the prior art. The operational amplifier 20 includes an input stage 21, an AB-class output stage 22, and a switched capacitor level shifter 23. The input stage 21 includes p-type transistor MP1-MP4, n-type transistors MN1-MN5, and a common mode feedback circuit 200. The output stage 22 includes p-type transistors MP6-MP7, n-type transistors MN6-MN9, the capacitors CM1, CM2, and a common mode feedback circuit 202. The switched capacitor level shifter 23 consists of switches S1-S16 and capacitors C1-C8, and is utilized for decoupling the input stage 21 and the output stage 22. By the use of the switched capacitor level shifter 23, the output common mode voltage of the input stage 21 is no longer determined by the input common mode voltage of the output stage 22, so that the headroom issue is solved. Bias voltages VBP1, VBP2, VBN1, and VBN2 are used in the input stage 21, and bias voltages VBP3, VBN3 and VC are used in the switched capacitor level shifter 23.
Compared to the operational amplifier 10, the operational amplifier 20 prevents the headroom issue that may happen in the input stage, but there are still some disadvantages left. For example, a lot of switches and capacitors and control circuit are required in the switched capacitor level shifter 23, which means a large cost. Note that, the transistors MN8 and MP8 in the common mode feedback circuit 202 operate as a common mode loop gain amplifier and produce a larger capacitive load, and lead to a smaller bandwidth, a smaller phase margin, and increasing instability. The operational amplifier 20 are restricted to be applied in the switched-capacitor type circuits as pipelined ADCs due to the switched capacitor level shifter 23, and cannot be used in continuous-time type circuits as active RC filters and programmable gain amplifiers (PGA).
The operational amplifier 10 can be used in a programmable gain amplifier. Please refer FIG. 3, which is a schematic diagram of a programmable gain amplifier 30 according to the prior art. The programmable gain amplifier 30 has an inherent DC offset cancellation function, and is widely used in the systems requiring high gain as a wireless communication system. The programmable gain amplifier 30 includes an operational amplifier 300, resistors R1-R4, RH1, RH2, capacitors CH1, and CH2, wherein the operational amplifier 300 is as the operational amplifier 10. The resistors RH1, RH2, the capacitors CH1, and CH2 forms a high-pass filtering circuit used for cancel DC offset voltage across differential output terminals of the operational amplifier 300. Assume that resistances of the resistors RH1 and RH2 are equal, denoted as RH, capacitances of the capacitors CH1 and CH2 are equal, denoted as CH, and resistances of the resistors R1 and R2 are R1 and R2, a transfer function of an output signal Vo to an input signal Vi of the programmable gain amplifier 30 is
                                                        V              o                                      V              i                                =                                                    R                2                                            R                1                                      ⁢                          1                              1                +                                                      1                    +                                                                  R                        2                                            /                                              R                        1                                                                              A                                                      ⁢                                                            sR                  H                                ⁢                                  C                  H                                                            1                +                                                      sR                    H                                    ⁢                                      C                    H                                                                                      ,                            (        1        )            where A is a gain of the operational amplifier 300. When A is large, the equation 1 can be simplified as follows:
                                                        V              o                                      V              i                                =                                                    R                2                                            R                1                                      ⁢                                                            sR                  H                                ⁢                                  C                  H                                                            1                +                                                      sR                    H                                    ⁢                                      C                    H                                                                                      ,                            (        2        )            where s is a complex frequency. A corner frequency of the high-pass filtering circuit is equal to 1/RHCH.
Please refer to FIG. 4, which is a schematic diagram of a programmable gain amplifier 40 with an inherent DC offset cancellation function according to the prior art. The programmable gain amplifier 40 includes operational amplifiers 400, 402, resistors R1-R6, RH1, RH2, capacitor CH1, and CH2. The programmable gain amplifier 40 utilizes an active integrator that consists of the operational amplifier 402, the resisters RH1, RH2, the capacitors CH1, and CH2 to perform high-pass filtering. Assume that resistances of the resistors RH1 and RH2 are equal, denoted as RH, capacitances of the capacitors CH1 and CH2 are equal, denoted as CH, a transfer function of an output signal Vo to an input signal Vi of the programmable gain amplifier 40 is identical to the equation 1 and the equation 2.
From the above, when the number of programmable gain amplifiers in a programmable gain amplifier series increases, the number of components for implementing the DC offset cancellation function increases correspondingly, which results in a large cost.